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CXB1818Q
Laser Diode Driver
Description The CXB1818Q is a high-speed monolithic Laser Diode Driver/Current Switch with ECL/PECL input level. Open collector outputs are provided at the output pins (Q, QBX) and have the capacity of driving modulation current of 50mAp-p at a maximum data rate of 622Mbps. Along with the modulation current generator there is the laser diode bias current generator which has capacity of sourcing up to 60mA (Bias). The laser diode bias current can be controlled by either a voltage or current into the bias adjust pin (BiasAdj) and the bias set pin (SBias), depending on how these pins are configured. Control of the bias current is achieved through the APC (Automatic Power Control) circuit. In order to avoid having a large current go through the laser diode, this IC also provides an Activity detector function for laser protection. The Activity detector circuit detects data edge transitions and if no data transition occurs after a certain period, then both the modulation and bias currents are shutdown. The bias currents are shut it down by in order to pull down the output voltage of APC OP.Amp. When the automatic shutdown is conducted, it is possible to select whether the laser diode alarm output is activated or not. Additionally, this IC has the DFF for the input signal correction and the internal Duty Cycle correction circuit that can control the falling edge of the input pulse up to a maximum of 1.0ns(Min.). Features * Maximum data rate (NRZ): 622Mbps * Alarm and Shutdown function * DFF for input signal correction * Input signal Duty cycle correction * Automatic Power Control (APC) for bias current * Activity detector function for laser protection * Alarm signal mask function during shutdown * Differential PECL inputs or AC coupled inputs 40 pin QFP (Plastic)
Applications * SONET/SDH: 622Mbps * Fibre channel: 531Mbps Absolute Maximum Ratings * Supply voltage VCC - VEE
* Input voltage VIN * Differential input voltage | VD - VDB | 0 to 2.5 * Bias output current 0 to 80 * SBias input/output current 0 to 5 * Bias control current IBset (Ibiasadj) 0 to 5 * Bbias control voltage VBset (Vbiasadj) 0 to 3 * Modulation output current 70 * Modulation adjust current IQset (Idrvadj) 0 to 15 * Storage temperature Tstg -65 to +150 Recommended Operating Conditions * DC supply voltage 3.14 to 3.46 VCC - VEE * Operating ambient temperature Ta -40 to +85 Structure Bipolar silicon monolithic IC
-0.3 to +6.0 VEE to VCC
V V V mA mA mA V mA mA C
V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E99227-PS
CXB1818Q
Block Diagram and Pin Configuration
MaskSel
SDNB
VCC2
SDN
RSB
VEE2 22
30
29
28
27
26
25
24
23
21 20 ClkB
Reference Generator
Vbb Gen.
D-FF Tset 31 MUX
VREF
32
Vref
Clk
RS
DB
D
19 18
FFSel ADCDis Timer
VCC6
33
In_ALM
17 16 DRV Cont 15 14 13 12
LDAlm LDAlmB VCC3 VEE3 WCompIn RsetPD
34 35 36 37 38 39 Bias Circuit
Duty Cycle Cont
CompB CompA DrvAdj DrvMon TM
APCOut
40 1 VCC4 2 VEE4 3 BiasAdj 4 SBias 5 Bias 6 VEE5 7 Q 8 NC 9 QBX 10 VEE1
11
VCC1
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CXB1818Q
Pin Description Pin No. 1 2 Symbol VCC4 VEE4 Typical pin voltage [V] DC 3.3 0
VCC
Equivalent circuit
Description Positive power supply for APC circuit. Negative power supply for APC circuit.
4 5
AC
3
BiasAdj
1.5 to 0 0mA to 2.5mA 0mA to 60mA 0 6mA to 30mA1 1.3 to 3.3 6mA to 50mA2 6mA to 30mA1 1.3 to 3.3 6mA to 50mA2 -- 0 3.3 --
Bias current setting.
4
SBias
260 3 10pF 240 VEE 8 30
Bias current setting or monitor. Bias current output. Open collector output. Negative power supply for bias circuit.
5
Bias
6
VEE5
7
Q
7
9
Modulation current output. Open collector output. Complementary current output. Q and QBX are not symmetrical output. Use Q output for laser diode. No connected. Negative power supply for driver circuit. Positive power supply for driver circuit.
VEE
9
QBX
Current Source VEE
8 10 11
NC VEE1 VCC1
12
TM
1.5
12
10
Chip temperature monitor. Modulation current (IQ) monitor. IQ is monitored by connecting a resistor (Rmon) to this pin. Modulation current (IQ) setting.
VCC
13
DrvMon
0mA to 1.4mA 0mA to 9mA
Rmon 14 13
14
DrvAdj
22.5 VEE
150
1 Ta = -40 to 0C 2 Ta = 0 to +85C -3-
CXB1818Q
Pin No.
Symbol
Typical pin voltage [V] DC AC
Equivalent circuit
Description
15
CompA
180pF
VCC 15 16 30pF
16
CompB
10k VEE
Modulation current driver compensation. Normally, connects 180pF capacitor between CompA and CompB pins.
VCC Ctimer 17 2.1k 100 2.4k 10pF 25A 200A 2.4k
17
Timer
VEE
Capacitor connection for activity detector (IN_ALM) operation. This pin sets the period of inactive time for activity detector. Inactive time is controlled by connecting a capacitor to this pin.
VCC 3.8k 3.8k
18
ADCDis
VEE to VCC (open)
18 VEE
35k 35k 35k 35k 15A
Activity detector circuit control. High (connected to VCC or open): Activity detector is disable. Low (connected to VEE): Activity detector is enable.
VCC 9k 4.5k 4.5k
19
FFSel
VEE or open
19 100k 4.5k 4.5k
VEE
Input data D-FF selection control. High (open): FF not used (Through mode) Low (connect to VEE): FF used (FF mode)
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CXB1818Q
Pin No.
Symbol
Typical pin voltage [V] DC AC
Equivalent circuit
Description
VCC
20
ClkB
1.6 to 2.4
20 200 21
550
550
200 400A
Differential PECL clock input.
21
Clk
1.6 to 2.4
VEE
22
VEE2
0
25 300 300
Negative power supply for data input circuit.
23
DB
1.6 to 2.4
24 200 23 200 10k 10k 300A
Differential PECL data input.
24
D
1.6 to 2.4
1mA 22
25
VCC2
3.3
Positive power supply for data input circuit. Alarm signal control for optical power output forced shutdown. High (open): Alarm signal is High for shutdown. Low (connect to VEE): Alarm signal stays Low for shutdown.
VCC 9k 4.5k 4.5k
26
MaskSel
VEE or open
1k 26 2.2k VEE 2.2k
VCC
27
RSB
0.5
28
100A 2.5k 15k 27
28
RS
2.0
VEE
5k
Window comparator top/bottom threshold voltage for LD_ALARM. The alarm (fault) assert voltage can be set by the external resistor. Default voltages are RS equal to 2.0V and RSB equal to 0.5V. (Option)
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CXB1818Q
Pin No.
Symbol
Typical pin voltage [V] DC AC
VCC
Equivalent circuit
Description
29
SDNB
0 to 3.3
300 29 30
5k
5k
5k
5k
300
Complementary TTL input to disable the output current. (Shutdown input) When left open, High.
60A
30
SDN
0 to 3.3
VEE
60A
VCC 2.4k 2.4k 20pF Rset 31
31
Tset
70A VEE 220 140
Output duty cycle control. This pin controls the falling edge of the input High pulse. Variable delay limit of that is from 0 to 1.0ns. Duty cycle is controlled by connecting a resistor value between VCC and this pin.
VCC 300 200 32 300
32
VREF
1.7
2.4k
9.1k VEE
1.9mA
Temperature compensated reference voltage for APC. Approximately 1.7V (Constant for VEE reference)
33
VCC6
3.3
Positive power supply for alarm output circuit.
34
LDAlm
0.2 to 3.0
VCC
34 35
Activates when the fault is detected in the laser monitor diode circuit. (Pseudo LVTTL output)
35
LDAlmB
0.2 to 3.0
VEE
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CXB1818Q
Pin No. 36 37
Symbol VCC3 VEE3
Typical pin voltage [V] DC 3.3 0
VCC
AC
Equivalent circuit
Description Positive power supply for signal detection circuit. Negative power supply for signal detection circuit.
550
550 RS
38
WCompIn
38 200 200 VEE
200 RSB
APC alarm signal control.
VCC 300 200 39 300
39
RsetPD
1.8mA VEE
Monitor PD connection.
VCC
40
APCOut
40
APC operational amplifier output. This signal controls the bias adjust pins. (BiasAdj and SBias)
500
VEE
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CXB1818Q
Electrical Characteristics DC Electrical Characteristics Item DC supply voltage Supply current Modulation output current range Modulation output voltage range Ratio of IQ vs. IQset Bias output current range Bias output voltage range Ratio of IB vs. IBset ECL input High voltage ECL input Low voltage SDN, SDNB input High voltage SDN, SDNB input Low voltage LDA, LDAB output High voltage LDA, LDAB output Low voltage Symbol Vdc IEE IQ1 IQ2 VQ IQ vs IQset IB VB IB vs IBset VEIH VEIL VTIH VTIL VTOH VTOL Iin = -0.4mA Iin = 2.0mA (VCC = 3.14 to 3.46V, VEE = 0V, Ta = -40 to +85C) Condition VCC - VEE IQ = 0mA, IBIAS = 0mA Ta = -40 to 0C Ta = 0 to +85C Min. 3.14 -80 6 6 VCC - 2 4 0 VCC - 2 14 VCC - 1.17 VCC - 1.84 2 0 2.4 -- 1.5 -500 Typ. 3.3 -57 -- -- -- 6 -- -- 22 -- -- -- -- -- -- 1.7 -- Max. 3.46 -- 30 50 VCC 9 60 VCC 28 VCC - 0.81 VCC - 1.48 VCC 0.8 -- 0.5 1.9 +500 A V Unit V mA mA V -- mA V --
Reference bias voltage for OP Amp VREF Operating current range of VREF VREFdrv
AC Electrical Characteristics Item Maximum data rate Rise time (20 to 80%) Fall time (20 to 80%) Max. variable High pulse width by duty cycle control Max. setting time of IN_Alarm Shutdown time Shutdown recovery time Maximum set up time Maximum hold time Symbol fdmax tr tf tdelay ts_alm tsut_off tsut_on TS TH
(VCC = 3.14 to 3.46V, VEE = 0V, Ta = -40 to +85C) Condition Min. 622 IQ = 20mA, RL = 25 IQ = 20mA, RL = 25 Data rate = 622Mbps 1.0 20 10 100 200 200 ps s 200 200 Typ. Max. Unit Mbps ps ns
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CXB1818Q
DC and AC Electrical Characteristics for OpAmp of APC Circuit (VCC = 3.14 to 3.46V, VEE = 0V, Ta = -40 to +85C) Item Input voltage range Output voltage range Input bias current Input offset voltage Input offset current Input impedance Output drive current Through rate Open loop gain Unity gain band width Symbol VIN VO IB VOFF IOFF ZIN IO SR Av funit Condition Min. 1.2 0.6 -- -- -- -- -5.0 -- -- -- Typ. -- -- 7 2.5 0.7 12 -- 1.9 55 20 Max. 2.8 2 -- -- -- -- 1.0 -- -- -- Unit V V A mV A k mA V/s dB MHz
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CXB1818Q
Description of Each Function Block 1. Data Buffer, Clock Buffer Data Buffer and Clock Buffer are comprised of the data buffer, clock buffer, DFF, MUX and delay generator. ECL/PECL data is input to the data buffer at a maximum data rate of 622Mbps. The input data DFF selection pin (Pin 19 FFSel) can select whether the input data is used in through mode or the signal which is corrected by the clock signal in the DFF is used. When the FFSel is open, the data becomes through mode, when the FFsel is connected VEE,the data becomes DFF mode. And, this data is input to the delay circuit. The delay circuit adds a delay to the falling edge of the pulse up to a maximum of 1.0ns for the D input signal High pulse (Q output current pulse). The delay is set by an external resistor between the delay set pin (Pin 31 Tset) and VCC. The relation between the High pulse width and the set resistance (Rset) is shown in Fig. 1. The Vbb generator provides a reference bias current to the data buffer for AC coupling inputs. 2. Modulation Current Generator This circuit modulates the laser diode and the modulation current can be set by feeding the current to the modulation current set pin (Pin 14 DrvAdj). The relation between the modulation current (IQ) and the modulation set current (IQset) is shown in Fig. 2. There is also a modulation current monitor pin (Pin 13 DrvMon) that allows the IC user to monitor the modulation current by putting an external fixed resistor between VCC and DrvMon pins, and the modulation current can be monitored by measuring the voltage of DrvMon pin. The relation between the modulation current (IQ) and the DrvMon current (Idrvmon) is shown in Fig. 7. 3. Laser Diode Bias Current Generator This circuit is a very large current source capable of sourcing up to 60mA of bias current to the laser diode. The circuit is a 22 to 1 (for current - current setting) current mirror that can be controlled externally two ways. The first method is to short BiasAdj (Pin 3) and SBias (Pin 4) together and inject a control current (IBset) into the two pins. Bias (Pin 5) is connected to the laser diode. Laser diode bias current vs. control current (IBset) characteristics is shown in Fig. 3. The second method is to tie SBias (Pin 4) to VCC and tune BiasAdj (Pin 3) with a voltage source. Varying the voltage at the BiasAdj pin will vary the current through the laser diode. Laser diode bias current vs. control voltage characteristics is shown in Fig. 4. 4. APC (Automatic Power Control) Circuit The APC circuit is comprised of the window comparator, APC OpAmp, and laser diode alarm circuit. The APC OpAmp is normally configured as an inverting integrator. The inverting input is connected to the photodiode that monitors the optical power output from the laser diode. The photodiode converts the optical power received from the laser diode to a current. The output of the OpAmp then drives the laser diode current bias adjust pin (BiasAdj), and the laser diode current bias set pin (SBias) is shorted to VCC via a resistor. With the OpAmp configured as an inverting integrator, the OpAmp can tune the laser diode current inversely to the current in the photodiode. That is to say that if a Low current is detected by the photodiode the integrator output goes up causing more bias current to flow through the laser diode. If the photodiode current is High, the output of the OpAmp will go Low causing less bias current to flow through the laser diode. When the output of the APC OpAmp (Pin 40 APCOut) is connected to the window comparator input pin (Pin 38 WCompIn), the function of the window comparator detects the voltage which is outside of the reference voltage range for each comparator (RS, RSB). When this happens, the comparator outputs cause the laser diode alarm output (LDAlm) to go High alerting the system that the laser diode current is in the outside of the range. - 10 -
CXB1818Q
The laser diode alarm output state can be controlled by the alarm signal control pin (Pin 26 MaskSel) for the optical power output forced shutdown. When the automatic shutdown is conducted and MaskSel pin is left open, the laser diode alarm output goes High. The laser diode alarm output is kept Low (disable) by connecting MaskSel pin to VEE. 5. Shutdown and Input Alarm Circuits These circuits disable both the modulation current and the bias current under various conditions. The function block diagram for all of the shutdown mechanisms for the circuit is shown in Fig. 5. The Shutdown circuit has complementary TTL input to disable the output current. Shown below is the desired truth table for the shutdown function. SDN Low Low High High SDNB Low High Low High Output current Off On Off Off
The Activity detector (In_ALM) circuit is designed to detect the input data edge transition. If there is no input data transition over a certain period determined by the user (TACT), the Shutdown circuit is enabled, causing the modulation current and bias current to be shutdown. The Inactive time (TACT) is set by the external capacitor value between Timer (Pin 17) and VCC. The relation between the Inactive time and Ctimer is shown in Fig.6.
SDN SDNB
Shutdown Switch To modulation and bias current Shutdown circuits
D DB
In_ALM
Timer ADCDis
Fig.5. Shutdown and In_ALM Functional Block Diagram
6. Others Pay attention to handling this IC because its electrostatic discharge strength is weak. The Tset pin (Pin 31) should be connected to VCC through a resistor. Do not leave this pin open or connect to VCC directly.
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CXB1818Q
DC Electrical Characteristics Measurement Circuit
V
30 29 28
V
27 26 25 24 23 22 21 20
Reference Generator
Vbb Gen.
D-FF 2k 31 -500 to +500A 32 Vref MUX 19 18 33 In_ALM 17 0.1F 16 DRV Cont 15 14 13 12 180pF
V
V
-0.4mA or +2.0mA 34 35 Duty Cycle Cont
V
36 37 38 1k 39 1k 40 Bias Circuit
A
V
11 1 2 3 4 5 6 7 8 9 10
V
A A
0 to -2V
A
25
A
3.14 to 3.46V
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CXB1818Q
AC Electrical Characteristics Measurement Circuit
PECL input 51 0.1F 30 29 28 27 26 25 24 23 51 0.1F 22 21
PECL input
PECL input
Reference Generator
Vbb Gen.
20
D-FF 31 100k 32 Vref MUX
19 18
33
In_ALM
17 0.1F 16 DRV Cont 15 14 13 12 1k 180p
34 35 36 37 38 39 1F Spectrum analizar 40 1F 1 2 3 4 5 6 Bias Circuit
Duty Cycle Cont
11 7 8 9 10
25
ZO = 50
3.14 to 3.46V
Osilloscope 50 input
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CXB1818Q
Application Circuit (at VCC = 3.3V, VEE = 0V)
SDN SDNB PECL input PECL input PECL input
30
29
28
27
26
25
24
23
22
21 20
Reference Generator
Vbb Gen.
100pF 31 Rset 32 Vref
D-FF
MUX
19 18
33
In_ALM
17 16 DRV Cont 15 14 13 12 180pF
Ctimer
LDAlm LDAlmB
34 35 36 37 38
Duty Cycle Cont
1k
Cpd Rf
39
Bias Circuit 11 1 2 3 4 5 6 7 8 9 10
40
R1
Rs
Iset
15
5.1
20
Rpd 3.3V
100pF
0.1F
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXB1818Q
Example of Representative Characteristics
2.8 2.6 2.4 Pulse width [ns] IQ [mA] 2.2 2.0 1.8 1.6 1.4 70 60 50 40 30 20 10 0 VQ = 0V VQ = -0.5V VQ = -1.0V VQ = -1.5V VQ = -2.0V
0
2
4
6 8 Rset [k]
10
12
14
0
2
4 6 IQset [mA]
8
10
Fig. 1. Pulse width vs. Rset characteristics when 1.6ns input data pulse (622Mbps) is applied
70 60 50 IBIAS [mA] IBIAS [mA] 40 30 20 10 0 70 60 50 40 30 20 10 0
Fig. 2. Modulation current (IQ) vs. IQset characteristics
0
0.5
1
1.5 2 IBset [mA]
2.5
3
0.4
0.6
0.8
1 1.2 VBset [V]
1.4
1.6
Fig. 3. Bias current (IBIAS) vs. Bias adjust current (IBset) characteristics
70
Fig. 4. Bias current (IBIAS) vs. Bias adjust voltage (VBset) characteristics
70 60 50 VQ = 0V VQ = -1V VQ = -2V
60 Input detection time [s]
50 IQ [mA] 40 30 20 10 0
40
30
20
10
0.5
1
1.5
2 2.5 3 Ctimer [nF]
3.5
4
4.5
0
0.2
0.4
0.6 0.8 1 Idrvmon [mA]
1.2
1.4
1.6
Fig. 6. Input detection time vs. Ctimer characteristics
Fig. 7. Modulation current (IQ) vs. DrvMon current characteristics
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CXB1818Q
VCC = 0V VEE = -3.3V RL = 25 Ta = 27C IQ = 30mA Single-phase input Pattern = PRBS223 - 1 Data Rate 622Mbps
Ch.1: 150mV/div Time Base: 500ps/div
Fig. 8. Electrical Output Waveform
2
1
VCC = 0V VEE = -3.3V FP - LD ( = 1330nm) Ta = 27C Single-phase input Pattern = PRBS223 - 1 Data Rate 622Mbps Filter (Cut Off 450MHz) Mask: STM4/OC12
3 Ch.2: 5.0mV/div Time Base: 500ps/div
Fig. 9. Optical Power Output Waveform
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CXB1818Q
Package Outline
Unit: mm
40PIN QFP (PLASTIC)
9.0 0.4 + 0.4 7.0 - 0.1 30 21
+ 0.35 1.5 - 0.15 + 0.1 0.127 - 0.05 0.1
31
20
A
40 1 0.65 + 0.15 0.3 - 0.1 + 0.15 0.1 - 0.1
11
10 0.24 M
0 to 10
0.5 0.2
(8.0)
PACKAGE STRUCTURE
PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.2g
DETAIL A SONY CODE EIAJ CODE JEDEC CODE QFP-40P-L01 QFP040-P-0707
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
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